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w78l52 8-bit microcontroller publication release date: january 1999 - 1 - revision a2 general description the w78l52 microcontroller supplies a wider frequency and supply voltage range than most 8-bit microcontrollers on the market. it is compatible with the industry standard 80c52 microcontroller series. the w78l52 contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable i/o port (port 4) and two additional external interrupts ( int2 , int3 ), three 16-bit timer/counters, one watchdog timer and a serial port. these peripherals are supported by a eight-source, two-level interrupt capability. there are 256 bytes of ram and an 8k byte mask rom for application programs. the w78l52 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. the idle mode turns off the processor clock but allows for continued peripheral operation. the power-down mode stops the crystal oscillator for minimum power consumption. the external clock can be stopped at any time and in any state without affecting the processor. features ? fully static design ? supply voltage of 1.8v to 5.5v ? dc-24 mhz operation ? 256 bytes of on-chip scratchpad ram ? 8k bytes of on-chip mask rom ? 64k bytes program memory address space ? 64k bytes data memory address space ? four 8-bit bidirectional ports ? three 16-bit timer/counters ? one full duplex serial port ? eight -source, two-level interrupt capability ? one extra 4-bit bit-addressable i/o port ? two additional external interrupts int2 / int3 ? watchdog timer ? emi reduction mode ? built-in power management ? code protection ? packages: ? dip 40: w78l52-24 ? plcc 44: w78l52p-24 ? qfp 44: w78l52f-24
w78l52 - 2 - pin configurations vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.5, a13 p2.6, a14 p2.7, a15 p2.0, a8 p2.1, a9 p2.2, a10 p2.3, a11 p2.4, a12 t2, p1.0 40-pin dip (w78l52) p1.2 p1.3 p1.4 p1.5 p1.6 rxd, p3.0 txd, p3.1 p1.7 rst int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal1 xtal2 vss t2ex, p1.1 44-pin plcc (w78l52p) 44-pin qfp (w78l52f) 40 2 1 44 43 42 41 6543 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 p4.1 p 4 . 0 int2, p4.3 / i n t 3 , p 4 . 2 34 40 39 38 37 36 35 44 43 42 41 33 32 31 30 29 28 27 26 25 24 23 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 1 8 7 6 5 10 9 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 p 4 . 0 / i n t 3 , p 4 . 2 p4.1 int2, p4.3
w78l52 publication release date: january 1999 - 3 - revision a2 pin description p0.0 ? p0.7 port 0, bits 0 through 7. port 0 is a bidirectional i/o port. this port also provides a multiplexed low order address/data bus during accesses to external memory. p1.0 ? p1.7 port 1, bits 0 through 7. port 1 is a bidirectional i/o port with internal pull-ups. pins p1.0 and p1.1 also serve as t2 (timer 2 external input) and t2ex (timer 2 capture/reload trigger), respectively. p2.0 ? p2.7 port 2, bits 0 through 7. port 2 is a bidirectional i/o port with internal pull-ups. this port also provides the upper address bits for accesses to external memory. p3.0 ? p3.7 port 3, bits 0 through 7. port 3 is a bidirectional i/o port with internal pull-ups. all bits have alternate functions, which are described below: pin alternate function p3.0 rxd serial receive data p3.1 txd serial transmit data p3.2 int0 external interrupt 0 p3.3 int1 external interrupt 1 p3.4 t0 timer 0 input p3.5 t1 timer 1 input p3.6 wr data write strobe p3.7 rd data read strobe p4.0 ? p4.3 another bit-addressable bidirectional i/o port p4. p4.3 and p4.2 are alternative function pins. it can be used as general i/o pins or external interrupt input sources ( int2 / int3 ). ea external address input, active low. this pin forces the processor to execute out of external rom. this pin should be kept low for all w78c32 operations. rst reset input, active high. this pin resets the processor. it must be kept high for at least two machine cycles in order to be recognized by the processor.
w78l52 - 4 - ale address latch enable output, active high. ale is used to enable the address latch that separates the address from the data on port 0. ale runs at 1/6th of the oscillator frequency. a single ale pulse is skipped during external data memory accesses. ale goes to a high impedance state during reset with a weak pull-up. psen program store enable output, active low. psen enables the external rom onto the port 0 address/data bus during fetch and movc operations. psen goes to a high impedance state during reset with a weak pull-up. xtal1 crystal 1. this is the crystal oscillator input. this pin may be driven by an external clock. xtal2 crystal 2. this is the crystal oscillator output. it is the inversion of xtal1. v ss , v dd power supplies. these are the chip ground and positive supplies. block diagram p3.0 ~ p3.7 p1.0 ~ p1.7 alu port 0 latch port 1 latch timer 1 timer 0 timer 2 port 1 uart xtal1 psen ale gnd vdd rst xtal2 oscillator interrupt psw instruction decoder & sequencer reset block bus & clock controller sfr ram address power control 256 bytes ram & sfr stack pointer b addr. reg. incrementor pc dptr temp reg. t2 t1 acc port 3 latch port 4 latch port 3 port 2 latch p4.0 ~ p4.3 port 4 port 0 port 2 p2.0 ~ p2.7 p0.0 ~ p0.7 int2 int3 watchdog timer 8k bytes rom
w78l52 publication release date: january 1999 - 5 - revision a2 functional description the w78l52 architecture consists of a core controller surrounded by various registers, five general purpose i/o ports, 256 bytes of ram, three timer/counters, one watchdog timer and a serial port. the processor supports 111 different opcodes and references both a 64k program address space and a 64 k data storage space. timers 0, 1, and 2 timers 0, 1, and 2 each consist of two 8-bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the tcon and tmod registers provide control functions for timers 0, 1. the t2con register provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2. the operations of timer 0 and timer 1 are the same as in the w78l51. timer 2 is a special feature of the w78l52: it is a 16-bit timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit c/t2 in t2con. timer 2 has three operating modes: capture, auto-reload, and baud rate generator. the clock speed at capture or auto-reload mode is the same as that of timers 0 and 1. clock the w78l52 is designed to be used with either a crystal oscillator or an external clock. internally, the clock is divided by two before it is used. this makes the w78l52 relatively insensitive to duty cycle variations in the clock. crystal oscillator the w78l52 incorporates a built-in crystal oscillator. to make the oscillator work, a crystal must be connected across pins xtal1 and xtal2. in addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from xtal1 to xtal2 to provide a dc bias when the crystal frequency is above 24 mhz. external clock an external clock should be connected to pin xtal1. pin xtal2 should be left unconnected. the xtal1 input is a cmos-type input, as required by the crystal oscillator. as a result, the external clock signal should have an input one level of greater than 3.5 volts when v dd = 5 volts. power management idle mode the idle mode is entered by setting the idl bit in the pcon register. in the idle mode, the internal clock to the processor is stopped. the peripherals and the interrupt logic continue to be clocked. the processor will exit idle mode when either an interrupt or a reset occurs. power-down mode when the pd bit of the pcon register is set, the processor enters the power-down mode. in this mode all of the clocks, including the oscillator are stopped. the only way to exit power-down mode is by a reset. reset the external reset signal is sampled at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is running. an internal trigger circuit in the reset line is used to deglitch the reset line when the w78l52 is used with an external rc network. the reset logic also has
w78l52 - 6 - a special glitch removal circuit that ignores glitches on the reset line. during reset, the ports are initialized to ffh, the stack pointer to 07h, pcon (with the exception of bit 4) to 00h, and all of the other sfr registers except sbuf to 00h. sbuf is not reset. new defined peripheral in order to be more suitable for i/o, an extra 4-bit bit-addressable port p4 and two external interrupts int2 , int3 have been added to either the plcc or qfp package. and description follows: 1. int2 / int3 two additional external interrupts, int2 and int3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80c52. the functions/status of these interrupts are determined/shown by the bits in the xicon (external interrupt control) register. the xicon register is bit-addressable but is not a standard register in the standard 80c52. its address is at 0c0h. to set/clear bits in the xicon register, one can use the "setb (/clr) bit" instruction. for example, "setb 0c2h" sets the ex2 bit of xicon. ***xicon - external interrupt control (c0h) px3 ex3 ie3 it3 px2 ex2 ie2 it2 px3: external interrupt 3 priority high if set ex3: external interrupt 3 enable if set ie3: if it3 = 1, ie3 is set/cleared automatically by hardware when interrupt is detected/serviced it3: external interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software px2: external interrupt 2 priority high if set ex2: external interrupt 2 enable if set ie2: if it2 = 1, ie2 is set/cleared automatically by hardware when interrupt is detected/serviced it2: external interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software eight-source interrupt informations: interrupt source vector address polling sequence within priority level enable required settings interrupt type edge/level external interrupt 0 03h 0 (highest) ie.0 tcon.0 timer/counter 0 0bh 1 ie.1 - external interrupt 1 13h 2 ie.2 tcon.2 timer/counter 1 1bh 3 ie.3 - serial port 23h 4 ie.4 - timer/counter 2 2bh 5 ie.5 - external interrupt 2 33h 6 xicon.2 xicon.0 external interrupt 3 3bh 7 (lowest) xicon.6 xicon.3
w78l52 publication release date: january 1999 - 7 - revision a2 2. port4 another bit-addressable port p4 is also available and only 4 bits (p4<3:0>) can be used. this port address is located at 0d8h with the same function as that of port p1, except the p4.3 and p4.2 are alternative function pins. it can be used as general i/o pins or external interrupt input sources ( int2 / int3 ). example: p4 reg 0d8h mov p4, #0ah ; output data "a" through p4.0 ? p4.3. mov a, p4 ; read p4 status to accumulator. setb p4.0 ; set bit p4.0 clr p4.1 ; clear bit p4.1 watchdog timer the watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. it is basically a set of dividers that divide the system clock. the divider output is selectable and determines the time-out interval. when the time-out occurs a system reset can also be caused if it is enabled. the main use of the watchdog timer is as a system monitor. this is important in real-time control applications. in case of power glitches or electro-magnetic interference, the processor may begin to execute errant code. if this is left unchecked the entire system may crash. the watchdog time-out selection will result in different time-out values depending on the clock speed. the watchdog timer will de disabled on reset. in general, software should restart the watchdog timer to put it into a known state. the control bits that support the watchdog timer are discussed below. watchdog timer control register bit: 7 6 5 4 3 2 1 0 enw clrw widl - - ps2 ps1 ps0 mnemonic: wdtc address: 8fh enw : enable watch-dog if set. clrw: clear watch-dog timer and prescaler if set. this flag will be cleared automatically widl : if this bit is set, watch-dog is enabled under idle mode. if cleared, watch-dog is disabled under idle mode. default is cleared. ps2, ps1, ps0: watch-dog prescaler timer select. prescaler is selected when set ps2 ? 0 as follows: ps2 ps1 ps0 prescaler select 0 0 0 2 0 1 0 4 0 0 1 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256
w78l52 - 8 - the time-out period is obtained using the following formula: 1 osc 2 prescaler 1000 12 ms 14 before watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to wdtc.6 (clrw). after 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. the watchdog timer is cleared on reset. osc 1/12 prescaler 14-bit timer clear clrw external reset internal reset widl idle enw watchdog timer block diagram typical watchdog time-out period when osc = 20 mhz ps2 ps1 ps0 watchdog time-out period 0 0 0 19.66 ms 0 1 0 39.32 ms 0 0 1 78.64 ms 0 1 1 157.28 ms 1 0 0 314.57 ms 1 0 1 629.14 ms 1 1 0 1.25 s 1 1 1 2.50 s reduce emi emission because of the on-chip rom, when a program is running in internal rom space, the ale will be unused. the transition of ale will cause noise, so it can be turned off to reduce the emi emission if it is not needed. turning off the ale signal transition only requires setting the bit 0 of the auxr sfr, which is located at 08eh. when ale is turned off, it will be reactivated when the program accesses external rom/ram data or jumps to execute an external rom code. the ale signal will turn off again after it has been completely accessed or the program returns to internal rom code space. auxr - auxiliary register bit: 7 6 5 4 3 2 1 0 - - -- - --ao mnemonic: auxr address: 8eh ao: turn off ale signal.
w78l52 publication release date: january 1999 - 9 - revision a2 absolute maximum ratings parameter symbol min. max. unit dc power supply v cc ? v ss -0.3 +7.0 v input voltage v in v ss -0.3 v cc +0.3 v operating temperature t a 070 c storage temperature t st -55 +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability o f the device. dc characteristics (v ss = 0v, t a = 25 c, unless otherwise specified.) parameter sym. specification unit test conditions min. max. operating voltage v dd 1.8 5.5 v operating current i dd - 20 ma no load v dd = 5.5v - 3 ma no load v dd = 2.0v idle current i idle -6mav dd = 5.5v, fosc = 20 mhz - 1.5 ma v dd = 2.0v, fosc = 16 mhz power down current i pwdn -50 a v dd = 5.5v, fosc = 20 mhz -20 a v dd = 2.0v, fosc = 16 mhz input current p1, p2, p3, p4 i in1 -50 +10 a v dd = 5.5v v in = 0v or v dd input current rst i in2 -10 +300 a v dd = 5.5v 0 < v in < v dd input leakage current p0, ea i lk -10 +10 a v dd = 5.5v 0v < v in < v dd logic 1 to 0 transition current p1, p2, p3, p4 i tl [*4] -500 - a v dd = 5.5v v in = 2.0v input low voltage v il1 0 0.8 v v dd = 4.5v p0, p1, p2, p3, p4, ea 0 0.5 v v dd = 2.0v input low voltage v il2 0 0.8 v v dd = 4.5v rst[*1] 0 0.3 v v dd = 2.0v
w78l52 - 10 - dc characteristics, continued parameter sym. specification unit test conditions min. max. input low voltage v il3 0 0.8 v v dd = 4.5v xtal1 [*3] 0 0.5 v v dd = 2.0v input high voltage v ih1 2.0 v dd +0.2 v v dd = 5.5v p0, p1, p2, p3, p4, ea 1.4 v dd +0.2 v v dd = 2.0v input high voltage v ih2 3.5 v dd +0.2 v v dd = 5.5v rst[*1] 1.7 v dd +0.2 v v dd = 2.0v input high voltage v ih3 3.5 v dd +0.2 v v dd = 5.5v xtal1 [*3] 1.6 v dd +0.2 v v dd = 2.0v output low voltage v ol1 - 0.45 v v dd = 4.5v, i ol = +2 ma p1, p2, p3, p4 - 0.25 v v dd = 2.0v, i ol = +1 ma output low voltage v ol2 - 0.45 v v dd = 4.5v, i ol = +4 ma p0, ale, psen [*2] - 0.25 v v dd = 2.0v, i ol = +2 ma sink current i sk1 49mav dd = 4.5v, vin = 0.45v p1, p2, p3, p4 1.8 5.4 ma v dd = 2.0v, vin = 0.4v sink current i sk2 816mav dd = 4.5v, vin = 0.45v p0, ale, psen 4.0 9 ma v dd = 2.0v, vin = 0.45v output high voltage v oh1 2.4 - v v dd = 4.5v, i oh = -100 a p1, p2, p3, p4 1.4 - v v dd = 2.0v, i oh = -8 a output high voltage v oh2 2.4 - v v dd = 4.5v, i oh = -400 a p0, ale, psen [*2] 1.4 - v v dd = 2.0v, i oh = -200 a source current i sr1 -100 -250 a v dd = 4.5v, vin = 2.4v p1, p2, p3, p4 -10 -30 a v dd = 2.0v, vin = 1.4v source current i sr2 -8 -16 ma v dd = 4.5v, vin = 2.4v p0, ale, psen -1.0 -2.4 ma v dd = 2.0v, vin = 1.4v notes: *1. rst pin is a schmitt trigger input. *2. p0, ale and /psen are tested in the external access mode. *3. xtal1 is a cmos input. *4. pins of p1, p2, p3, p4 can source a transition current when they are being externally driven from 1 to 0.
w78l52 publication release date: january 1999 - 11 - revision a2 ac characteristics the ac specifications are a function of the particular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the internal routing capacitance. most of the specifications can be expressed in terms of multiple input clock periods (t cp ), and actual parts will usually experience less than a 20 ns variation. the numbers below represent the performance expected from a 0.5 micron cmos process when using 2 and 4 ma output buffers. clock input waveform t t xtal1 f ch cl op, t cp parameter symbol min. typ. max. unit notes operating speed f op 0 - 24 mhz 1 clock period t cp 25 --ns 2 clock high t ch 10 --ns 3 clock low t cl 10 --ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a reference in other specifications. 3. there are no duty cycle requirements on the xtal1 input. program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t cp - ? --ns4 address hold from ale low t aah 1 t cp - ? - - ns 1, 4 ale low to psen low t apl 1 t cp - ? --ns4 psen low to data valid t pda --2 t cp ns 2 data hold after psen high t pdh 0 -1 t cp ns 3 data float after psen high t pdz 0 -1 t cp ns ale pulse width t alw 2 t cp - ? 2 t cp - ns 4 psen pulse width t psw 3 t cp - ? 3 t cp -ns4 notes: 1. p0.0 ? p0.7, p2.0 ? p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internally prior to psen going high. 4. " ? " (due to buffer driving delay and wire loading) is 20 ns.
w78l52 - 12 - data read cycle parameter symbol min. typ. max. unit notes ale low to rd low t dar 3 t cp - ? - 3 t cp+ ? ns 1, 2 rd low to data valid t dda --4 t cp ns 1 data hold from rd high t ddh 0-2 t cp ns data float from rd high t ddz 0-2 t cp ns rd pulse width t drd 6 t cp - ? 6 t cp -ns2 notes: 1. data memory access time is 8 t cp . 2. " ? " (due to buffer driving delay and wire loading) is 20 ns. data write cycle parameter symbol min. typ. max. unit ale low to wr low t daw 3 t cp - ? - 3 t cp + ? ns data valid to wr low t dad 1 t cp - ? --ns data hold from wr high t dwd 1 t cp - ? --ns wr pulse width t dwr 6 t cp - ? 6 t cp -ns note: " ? " (due to buffer driving delay and wire loading) is 20 ns. port access cycle parameter symbol min. typ. max. unit port input setup to ale low t pds 1 t cp --ns port input hold from ale low t pdh 0--ns port output to ale t pda 1 t cp --ns note: ports are read during s5p2, and output data becomes available at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference.
w78l52 publication release date: january 1999 - 13 - revision a2 timing waveforms program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar
w78l52 - 14 - timing waveforms, continued data write cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds
w78l52 publication release date: january 1999 - 15 - revision a2 typical application circuits expanded external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 27512 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74hc373 ad0 ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 16 psen 29 ale 30 txd 11 rxd 10 w78l52 10 u 8.2 k dd crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 v dd v figure a crystal c1 c2 r 16 mhz 30p 30p ? 24 mhz 15p 15p ? 33 mhz 10p 10p 6.8k 40 mhz 5p 5p 4.7k above table shows the reference values for crystal applications. note: c1, c2, r components refer to figure a.
w78l52 - 16 - typical application circuits, continued expanded external data memory and oscillator 10 u 8.2 k dd oscillator ea 31 xtal1 19 xtal2 18 rst 9 int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 12 13 14 15 1 2 3 4 5 6 7 8 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 39 38 37 36 35 34 33 32 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 17 wr 16 psen 29 ale 30 txd 11 rxd 10 w78l52 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a0 a1 a2 a3 a4 a5 a6 a7 d0 q0 2 d1 q1 5 d2 q2 6 d3 q3 9 d4 q4 12 d5 q5 15 d6 q6 16 d7 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 3 4 7 8 13 14 17 18 q7 19 oc 1 g 11 74hc373 a0 a1 a2 a3 a4 a5 a6 a7 10 9 8 7 6 5 4 3 a0 a1 a2 a3 a4 a5 a6 a7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a14 25 24 21 23 26 1 20 2 a8 a9 a10 a11 a12 a13 a14 ce gnd 21 22 23 24 25 26 27 28 a8 a9 a10 a11 a12 a13 a14 gnd 22 27 oe wr 20256 v dd v figure b package dimensions 40-pin dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 a b c d e a l s a a 1 2 e b 1 1 e e 1 a 2.055 2.070 52.20 52.58 015 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2
w78l52 publication release date: january 1999 - 17 - revision a2 package dimensions, continued 44-pin plcc 44 40 39 29 28 18 17 7 61 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a e h e l y b c d a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 44-pin qfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.254 0.101 0.010 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.152 --- 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.025 0.063 0.003 0 7 0.394 0.031 0.398 0.037 9.9 0.80 0.65 1.6 10.00 0.8 10.1 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.2 12.95 10.1 10.00 9.9 7 0 0.08 0.031 0.01 0.02 0.25 0.5 --- --- --- --- --- 2 0.025 0.036 0.635 0.952 0.530 0.520 0.510 13.45 13.2 12.95 0.051 0.075 1.295 1.905
w78l52 - 18 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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